| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 170 | Establishing a Power and Time Optimized Serial Communication Link for High-end Transceivers Authors:A.SUSMITHA, CH.BALAKRISHNA, A.ENOCH |
0920-0923 |
Download | |
| IJVDCS 171 | A New Approach for Power and Latency Reduction by using C-Element in Digital Integrated Circuits Authors:KUNAM DIVYA, AZMEE RAVI |
0924-0927 |
Download | |
| IJVDCS 172 | Design of an Error Detection and Data Recovery Architecture for Motion Estimation Computing Array Authors:D.LEELA BHUVANESWRI, V.AMARESWAR |
0928-932 |
Download | |
| IJVDCS 173 | An Implementation of Assertion Based Verification (ABV) Algorithm for DDR Memory Cores Authors:KORUKONDA SAILESH, S.Ranjitha |
0933-0936 |
Download | |
| IJVDCS 174 | Realization of 32-Bit Unsigned Multiplier using CLAA CSLA and Spanning Tree Adder for High Speed Operations Authors:D.S.REVATHI, CHAYA SHANKAR |
0937-0942 |
Download | |
| IJVDCS 175 | Reduced-Complexity Reed–Solomon Encoder Based on Galois Field Authors:PULLAKANTI ASHALATHA, V.DAMODAR |
0943-0949 |
Download | |
| IJVDCS 176 | Implementation of Low power and High Speed Array Multiplier Using Bi-CMOS Technology for Driving Large Load Authors:VENNALA VASAVI, D.KHALANDAR BASHA |
0950-0954 |
Download | |
| Prev | 4 |
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