Design and Analysis of Approximate Compressors for Multiplication

Authors:K.MICHALRAJU

0767-0771

Effective Implementation of AES Algorithm using Reversible Logic

Authors:C.V. KAVYA SUVARCHALA

0772-0776

A Review On Montgomery Standard Multiplication using Low-Cost Superior VLSI Design

Authors:SAI ABHILASH KALAVAKURU, V.RAMESH

0777-0780

An Efficient Fault Tolerant Parallel Filters Based on Error Correction Codes

Authors:B. UMADEVI, RAMESH BABU

0781-0788

An Efficient Performance of Aging-Aware Variable-Latency Multiplier Design with the AHL

Authors:K.AMITHA SREE, B.UDAY KIRAN REDDY

0789-0794

Partially Parallel Decoding Architecture for Long Polar Codes

Authors:K. JAYA LAKSHMI, P. RAVI KUMAR

0795-0798

Design and Implementation of Fixed Point and Floating Point PID Controllers in VIVADO HLS using FPGA

Authors:K. ARUNA, J. BHASKARARAO

0799-0804

Design and Implementation of Carry Skip Adder using AOI and OAI

Authors:S. M. PADMAVATHI, N. RAVIKUMAR, VENTRAPRAGADA TEJU

0805-0809

Aging-Aware Variable-Latency Multiplier Based On the Column or Row by Passing Multiplier with Adaptive Hold Logic

Authors:B. MAHESH, NAMPALLY RAMESH, V. TEJU

0810-0816

Design and Implementation of Intelligent Controller Algorithms by Tuning of IPID Core

Authors:K. ANUSHAYADAV, DR. SHAIK MASTAN VALI

0817-0821