| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 160 | An Efficient Filter Based Multicarrier System Authors:POLASANI LAXMI, A. SANYASI RAO |
0872-0876 |
Download | |
| IJVDCS 161 | An Improved Controller Architecture for High Sped Memory Operations Authors:GUJJALA NARESH KUMAR, V.DAMODAR |
0877-0882 |
Download | |
| IJVDCS 162 | A High Efficiency Architecture for 16-Point Radix-4 Complex FFT Core using NEDA Authors:V. VENKATASESAIAH, M.SATHISH KUMAR |
0883-0886 |
Download | |
| IJVDCS 163 | Low-Complexity Reliability Based Fault Detection and Correction Circuits Authors:ALAGIRI LOKANATH, GUTHA VISWANATH |
0887-0892 |
Download | |
| IJVDCS 164 | Architecture for Robust Router Authors:PUJARI SREE DIVYA, R.ASHOK |
0893-0894 |
Download | |
| IJVDCS 165 | Designing of FFT/IFFT Processor for Wireless Communication Authors:ARRA RAMYA SUDHA, K.AMARENDER |
0895-0898 |
Download | |
| IJVDCS 166 | Design and Implementation of Different Quaternary Signed Digit Adder Authors:S.GOPI KRISHNA, A.RAM KUMAR |
0899-0905 |
Download | |
| IJVDCS 167 | Design and Implementation of 32 Bit Unsigned Multiplier Using Conditional Sum Adder Authors:G.RAJU, A.RAM KUMAR |
0906-0912 |
Download | |
| IJVDCS 168 | Designing an Efficient and High Throughput MIMO-OFDM System Authors:BOJJA AJAY BABU, VENAKATARAMI REDDY |
0913-0915 |
Download | |
| IJVDCS 169 | An Efficient and Area Optimized Fused FFT Processor for High end Transceivers Authors:K.DEEPTHI VATSALYA, P.SUDHAKAR RAO |
916-919 |
Download | |
