Implementation of Power Efficient Functional Broadside Tests with BIST Technique and Shared Logic

Authors:MOHAMMAD RIAZ, CH.CURY, D.SAILAJA

0712-0717

Low-Power Differential Logic Gates for DPA Resistant Circuits

Authors:IMMADISETTY BHAGYALAKSHMI, B. AJANTA REDDY

0718-0724

Realization of an Area Delay Product Optimized LMS Filter

Authors:PATHAN.ASIYA, K.GAYATHRI, D.SAILAJA

0725-0730

Design and Implementation of Efficient Adders for Arithmetic Applications for Reducing Area & Delay

Authors:PARISAPOGU PRIYANKA, M.RAJU

0731-0734

Comparative Analysis of FIR Filter for High Speed and Power Critical Applications

Authors:SAMALA ANUSHA, N.SURESH, D.SAILAJA

0735-740

Power Optimized Implementation of FM0/Manchester Encoding Architecture

Authors:SHAIK ARSHIYA SULTANA, S.MADHAVI, D.SAILAJA

0741-0746

Realization of Power Optimized RNS Architecture for Security Based Applications

Authors:ERAMALLA HEMALATHA, S.MADHAVI, D.SAILAJA

0747-0751

Design of Ultra-Low Power Capacitor Free-Low Dropout Regulator with Assistant Push-Pull Output Stage Circuit

Authors:P.SINDHU, S.HANUMANTHA RAO

0752-0756

Performance Analysis of a Low-Power High Speed Hybrid Full Adder Circuit

Authors:NARU VENKATA MAHIDHAR REDDY, C.VENKATAIAH

0757-0760

Realization of Low Power and High Speed Wide Multiplier Architecture Using D-Latch and Wallace Tree Multiplier

Authors:MANORAMA PADHY, DR. SUSHANT KUMAR MANDAL

0761-0766