| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 213 | Low Power Variable Latency Multiplier with AH Logic Authors:CH. N. V. SUBBA RAO, K. AMRUTHA VALLY |
1268-1271 |
Download | |
| IJVDCS 214 | High Speed Radix-10 Multiplication using Redundant BCD Codes Authors:VUTLA APARNA, BALA MURALI KRISHNA |
1271-1278 |
Download | |
| IJVDCS 215 | Design and Analysis of Low Power Pulse Triggered Flip-flop Based on Single Feed-Through Scheme Authors:Y.RAVALI, N.HARITHA |
1279-1283 |
Download | |
| IJVDCS 216 | An Overview of Advance Microcontroller Bus Architecture Relate on AHB Bridge Authors:K. VAMSI KRISHNA, K.AMARENDRA PRASAD |
1284-1288 |
Download | |
| IJVDCS 217 | Design of a 64-Bit Quantum Comparator using Reversible Logic Authors:TELLA VAJRA DEEPTHI, Y.SUJATHA |
1289-1296 |
Download | |
| IJVDCS 218 | Split-SAR ADCs: Improved Linearity with Power and Speed Optimization Authors:TOMPALA LAKSHMI, SANKARA RAO PALLA |
1297-1301 |
Download | |
| IJVDCS 219 | Design and Simulation of Low Voltage CMOS Comparator with Reduced Latency Authors:D.SINDHU, K.DEVI BHAVANI |
1302-1306 |
Download | |
| IJVDCS 220 | Design and Simulation of Reduced Static Power Dissipation in 12T SRAM by using DTCMOS Technique Authors:YERUKONDA SATYA SUREKHA, G. RAMA NAIDU |
1307-1310 |
Download | |
| IJVDCS 221 | Linear Precoder Design to Minimize Peak to Average Power Ratio (PAPR) For MIMO-OFDM System Authors:S. SURESH KUMAR, CH. MOHANA KRISHNA |
1311-1314 |
Download | |
| IJVDCS 222 | Design and Analysis of Mergable Flipflops for Carry Look Ahead Adder Authors:MADARAPU SANDEEP, SUMALINI |
1315-1318 |
Download | |
