Implementation of Power Optimized PRPG with Low Transition Test Compression Technique

Authors:INDRANI PASUPULETI, RAHUL VARMA DANTULURI

1217-1223

VLSI Implementation of High Throughput Pipelined Architecture for AES Algorithm

Authors:DR. R. V. KSHIRSAGAR, M. V. VYAWAHARE

1224-1228

Logical Effort Based Dual Mode Logic Gates

Authors:ARIGA MALLIKA, POTTI BALA MURALI KRISHNA

1229-1235

Design and Simulation of Arithmetic and Logic Unit using GDI Technology

Authors:P. ANIL KUMAR, E. NARENDRA

1236-1238

Implementation and Verification of I2C Single - Master Multiple Slave Bus Controller using System Verilog and UVM

Authors:SANGEPU BABY DHIVYA, DR. G. L. MADHUMATI

1239-1243

Design of Energy Efficient, Low PDP Full Subtractor using GDI Technique

Authors:S. SARAVANA, D. KRISHNA NAIK, DR. V. VIJAYALAKSHMI

1244-1248

Advanced Reducing Power Consumption in DRAM using Partial Access Method

Authors:D. RAKESH, P. RAJINI

1249-1253

Accuracy-Configurable Full Adders for Signal Processing Applications Design

Authors:V.SANTHOSHI, SOLMANRAJU PUTTA

1254-1257

Integration of Power Gating and Adiabatic Technique for Low Power Circuits Design

Authors:SRAVANI GUJJU, RAMU .M

1258-1263

Reduction of Static Losses in Full Subtractor using MTCMOS Technique

Authors:PASUPULETI SWATHI, T. SANDEEP GOUD

1264-1267