| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 144 | Design of FSM Oriented Open Core Protocol for Multi Stage Interconnection Network Authors:N. SRIKANTH, K. SURESH KUMAR |
0748-0751 |
Download | |
| IJVDCS 145 | High Performance MAC Architecture using Parallel Self Timed Adder Authors:B. LOKESH, S. ASHMAD, G. SRINIVASULU |
0752-0757 |
Download | |
| IJVDCS 146 | Implementation of Non-Fracturable and Fracturable with Varying MUX/LUT Authors:A. HARISH, S. ANJANEYULU |
0758-0761 |
Download | |
| IJVDCS 147 | Input Based Dynamic Reconfiguration for Low Power Image Processing and Secure Transmission Authors:JADI RAJU, MD. SHABAZKHAN, G. LAXMI NARAYANA |
0762-0768 |
Download | |
| IJVDCS 148 | A Reconfigurable High Speed Dedicated BISR Scheme for Repair Intra Cell Faults in Memories Authors:AMGOTH SRINIVAS, DR. A. BALAJI NEHRU, V. SUMATHI |
0769-0774 |
Download | |
| IJVDCS 149 | Reversible Logic using Area Efficient Improved Signed Digit Representation Approach for Constant Vector Multiplication Authors:M.VENKATESULU, P.JAYA RAMI REDDY, C. KUMAR |
0775-0780 |
Download | |
| IJVDCS 150 | Implementation of Efficient CSLA using D-LATCH Approach Authors:BANAVATHU VIJAYABABU NAIK, R. PRASAD RAO |
0781-0785 |
Download | |
| IJVDCS 151 | VLSI Realization of Hamming Logic Based Error Corrected Parallel Filters Authors:SURAPATHI RAMU, K.KALAPRIYA |
0786-0790 |
Download | |
| IJVDCS 152 | Realization of RISC Based Flexible DSP Processor for Power Critical Applications Authors:RAGHUMANDA SANTOSH, R. ANEEL KUMAR |
0791-0795 |
Download | |
| IJVDCS 153 | Aging Aware Reliable Multiplier with Adaptive Hold Logic Authors:K. SUPRAJA, B. JYOTHI |
0796-0801 |
Download | |
