Hardware Implementation of Image Deblurring Algorithm on FPGA

Authors:I. PRATHYUSHA, MOHAMMAD ZUBAIR

1165-1168

Implementation of Speed Optimized CSLA Architecture using D-Latch Approach

Authors:G. SOUJANYA, M. KEDARESWARA RAO

1169-1172

Matrix Based 128-Bit CRC Generation Architecture for High Speed Application

Authors:ASHOK BABU AMUDAPAKULA, DR. CH. BALASWAMY, DR. K. VEERA SWAMY

1173-1177

Novel Design for Authentication of Cryptographic Circuits Security using VLSI

Authors:S. SRAVANI, K. JAYASREE, H. CHANDRASEKHAR, L. RAMAMURTHY

1178-1183

Development of Versatile Multiplexer Logic

Authors:T. HARNATH, K. LAL KISHORE

1184-1191

Power Saving Topologically-Compressed with 21Transistor’s Flip-Flop using Multi Mode Switches

Authors:CHODISETTY V M KUMAR, BULASALA UMASANKAR

1192-1198

Speed and Area Optimized Realization of 5 Port Router using Verilog HDL

Authors:PANDIPATI PRASANTKUMAR, E. GOVIND

1199-1202

Evaluation of Sparse Tree RSFQ Adder for High Speed Applications

Authors:CHOUTAPALLI PRATHYUSHA, T. PATTALUNAIDU

1203-1207

Design of Fault Coverage Circuit with Efficient Hardware for Low Power Testing Applications

Authors:BANDI RENUKA, RONGALI ANEEL KUMAR

1208-1212

Realization of Multi-Operand Adders Based 64-Bit Modified Wallace MAC

Authors:PONNANA PRABHAVATHI, P. ASHOK

1213-1216