Implementation of Symmetric Transparent Online BIST for Arrays of Word-Organized RAMs

Authors:MOHAMMED AWAIS AHMED, SYED KHAJA AHMEDUDDIN ZAKIR

0618-0623

Design of High Speed Low Power 32-Bit Multiplier using Reversible Logic: A Vedic Mathematical Approach

Authors:R.VASIM AKRAM, MOHAMMED RAHMATULLAH KHAN, B.RAJKUMAR

0624-0629

Design of Delay Efficient 16-Bit Sparse-Tree Adder using Parallel Algorithm

Authors:A.VIJITHA, K.SAMPATH KUMAR, P.PRASHANTI

0630-0635

High Speed 8-Bit Vedic Multiplier using Barrel Shifter by Nikhilam Sutra

Authors:HINGE MAHESH, V. HANUMAN PRASAD

0642-0646

Designing of Multiband Clock Distribution using Verilog HDL

Authors:KRANTHI KUMAR MADASU, JARUPULA UMESH RAO

0647-0651

Faithfully Rounded Truncated Constant Multiplication/Accumulation for High Speed Fir Filter Designs

Authors:RAMANNA.LURRI, JARUPULA UMESH RAO

0652-0655

Design and Implementation of QSD Adders for Arithmetic Operation

Authors:N. LAVANYA, P. VIJETHA

0656-0661

Reducing Delay in Parallel Digital Filter Structure for Symmetric Convolution by using CSA Adder

Authors:A. HATHEERAM, N. BHOJANNA

0662-0665

Implementation and Optimization of CORDIC Design Through Fixed Angle of Rotation

Authors:BOMMADEVARA BHAGYASRI, DR. M.GURUNADHA BABU

0666-0673

Design of the Efficient Digital CMOS Comparator using Parallel Prefix Tree

Authors:S.MAHESH BABU, J NIRMALA BAI, DR.M.GURUNADHA BABU

0674-0680