| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 102 | Designing of Multiband Clock Distribution using True Single Phase Clock for SOC Authors:CH.MADAN, R.RAMESH BABU |
0560-0564 |
Download | |
| IJVDCS 103 | High Speed and Power Optimized Implementation of Carry Select Adder Authors:V.MADHURI, ANIL KUMAR GONA |
0565-0570 |
Download | |
| IJVDCS 104 | Speed and Area Optimized Implementation of EDDR Architecture Authors:V.MALLIKARJUNA RAO, PALAKOLANU SREEKANTHAREDDY |
0571-0577 |
Download | |
| IJVDCS 105 | Urdhva-Tiryagbhyam Sutra Multiplier Implementing by Reversible Gate Logic Authors:D. SHAVALAIAH, M. HANUMANTHU |
0578-0581 |
Download | |
| IJVDCS 106 | SYED JAFFAR ALI1, B.RAJ KUMAR2 Authors:SYED JAFFAR ALI, B.RAJ KUMAR |
0582-0587 |
Download | |
| IJVDCS 107 | An Area Efficient Enhanced Carry Select Adder Authors:GAANDLA.ANUSHA, B.SHIVA KUMAR |
0588-0592 |
Download | |
| IJVDCS 108 | Design of a Hybrid Adder using QCA Authors:S.PRATHYUSHA, K.SHAILAJA |
593-596 |
Download | |
| IJVDCS 109 | Design and Analysis of a Novel Low -Power SRAM for High Speed VLSI Design Authors:PUJARI MOUNIKA, MAHESH MUDAVATH |
0597-0599 |
Download | |
| IJVDCS 110 | A Modern Method for Detecting Cracks in Railway Tracks by the Efficient Utilization of LDR And LED System Authors:PRASHANTH.ADDAGATLA, G.KOTESHWAR RAO |
600-603 |
Download | |
| IJVDCS 111 | Design and Operation of Parallel Carry-Save Pipelined RSFQ Multiplier for Digital Signal Processing Authors:G.PRATHEEPA, D.MAHESH KUMATR |
0604-0608 |
Download | |
