Implementation of Error Correcting Codes for Low Area and Power Optimized Applications

Authors:SUNKARA KISHORE, G.SIVARAMAKRISHNA, K. CHINNAMALLA REDDY

0395-0400

Recursive Approach to the Design of CSLA D-Latch Based Parallel Self Timed Adder

Authors:K.SRI HARI, GOPI ALOKAM, L.CHANDRA SEKHAR

0401-0406

Optimization of Power in Flip-Flop Group using Clock Gating and Power Gating with Variable Body-Bias Technique

Authors:TASKEEN KAUR DHANJAL, APARNA KARWAL

0407-0411

Adaptive Procedure for Automatic Modulation Recognition

Authors:SALIVENDRA SUBRAHMANYA SASTRY, M. CHANDRA SHEKAR

0412-0415

Optimizing Data Encoding Schemes to Reducing Energy Consumption in Network on Chip

Authors:PRAMOD.BATHULA, IKKURTHI RAMAKOTESWARARAO

0416-0420

Design of 32-Bit Carry Look Ahead Adder using CNTFET Technology

Authors:G.BHARGAV, G.PRAASD.ACHARYA

0421-0426

Design of Inverter Based Double-Tail Comparator using CMOS Technology

Authors:POOJA JOSHI, APARNA KARWAL

0427-0430

An Expert Discrete Wavelet Adaptive Network Based Fuzzy Inference System for Digital Modulation Recognition

Authors:SALIVENDRA SUBRAHMANYA SASTRY, M. CHANDRA SHEKAR

0431-0435

Realization of Add-Multiply Operator using Power Optimized Modified Booth Recoder

Authors:P. GOWRI SWETHA

0436-0441

Design and Implementation of Wallace Tree Multiplier using Higher Order Compressors

Authors:DHANYA M RAVI

0442-0448