| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 174 | Design and Implementation of Low Power VLSI Circuit using VHDL Authors:P. RAHUL REDDY, D. PRASAD |
0945-0951 |
Download | |
| IJVDCS 175 | Design of Low Power, Area Efficient and High Speed 3-Bit Decoder Authors:CHAITRA B B |
0952-0956 |
Download | |
| IJVDCS 176 | VLSI Implementation of a High Speed Single Precision Floating Point Multiplier using Verilog Authors:GUNTUKA SWETHA, V. SANDEEP KUMAR |
0957-0961 |
Download | |
| IJVDCS 177 | FPGA Implementation of High Speed 8-Bit Vedic Multiplier using Barrel Shifter Authors:GURRAM SRAVANTHI, B.KISHORE BABU |
0962-0965 |
Download | |
| IJVDCS 178 | Design and Estimation of Delay, Power and Area for Parallel Prefix Adders Authors:NERADI GANGADHAR, P.ASHOK KUMAR |
0966-0971 |
Download | |
| IJVDCS 179 | Enhanced Area Efficient Architecture for 128 BIT Modified CSLA Authors:PAYYAVULA SWATHI, B. KISHORE BABU |
0972-0975 |
Download | |
| IJVDCS 180 | A Novel Fault Detection and Correction Technique for Memory Applications Authors:RAJKUMAR JARPULA, Y.SINGARAIAH |
0976-0981 |
Download | |
| IJVDCS 181 | High Speed Convolution and Deconvolution Algorithm (Based on Ancient Indian Vedic Mathematics) Authors:K. LEELA SANTHISHI, B. MUNILAKSHMI |
0982-0985 |
Download | |
| Prev | 4 |
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