| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 103 | A New Approach On Efficient Retiming of Fixed-Point Circuits Authors:S. VENU MADHAVI, S. BHAVANI, K. VIJAYA PRASAD |
0520-0523 |
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| IJVDCS 104 | The Design of Split Radix FFT Processor using Multi Bit Flip Flop for Power Reduction Authors:B. BALAJI, P. SYAMALA DEVI |
0524-0528 |
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| IJVDCS 105 | A Highly Parallel Area Efficient S-Box Architecture for Triple AES Byte Substitution Authors:V. JAYASREE, CH. PALLAVI, DR. M. JANARDHANA RAJU |
0529-0533 |
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| IJVDCS 106 | A Butterfly Architecture Based on Binary Signed-Digit Representation of Floating-Point Authors:I. PRADEEP KUMAR, P. RAJYALAXMI, K. VIJAYA PRASAD |
0534-0537 |
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| IJVDCS 107 | A New Design for VLSI Convolutive Blind Source Separation Authors:K. SANDEEP, M. VAISHNAVI, K. VIJAYA PRASAD |
0538-0542 |
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| IJVDCS 108 | An Error Resilient Approximate Parallel FFTs using Sum of Square And Error Correction Codes Authors:D. ESWARA RAO, R. SUNIL, K. VIJAYA PRASAD |
0543-0546 |
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| IJVDCS 109 | The Implementation of Reconfigurable Cordic Transactions Briefs Authors:K. MOUNIKA, P. RAJYALAXMI, K. VIJAYA PRASAD |
0547-0551 |
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| IJVDCS 110 | VLSI Architecture Low-Cost High-Performance for Montgomery Modular Multiplication Authors:V. NAVYA LAKSHMI, P. DEEPIKA, K. VIJAYA PRASAD |
0552-0555 |
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| IJVDCS 111 | A Generalized Algorithm and Efficient Architecture for Mixed-Decimation MDF Structure for Radix-2k Parallel FFT Authors:SK. KARISHMA, K. DHANUNJAYA |
0556-0563 |
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| IJVDCS 112 | Optimized Low Power Pseudo-Functional Scan-Based BIST for Delay Fault Using LP-LFSR Authors:SATISH KUMAR POTHULA, N.G N PRASAD |
0564-0570 |
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