| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 164 | Cordic Design using Sharing Shift and Add Method Authors:MUSHAM NAVANEETHA, J.VISHNUMURTHY, K.HYMAVATHI |
0883-0891 |
Download | |
| IJVDCS 165 | Error Detection and Correction using STI in Cache Memory Authors:D. VISHWAKALA, CH. SURESH, K. HYMAVATHI |
0892-0896 |
Download | |
| IJVDCS 166 | Effective Static Power Reduction Using Variation Tolerant Reconfigurable Multi mode Switches Authors:J. SAI PRIYADARSHINI, C. MADHU |
0897-0902 |
Download | |
| IJVDCS 167 | An Adaptive Low Latency Low Complexity Architecture for Matching of Information Coded with Error–Correcting Codes Authors:A. SATHVIKA, SYED MUSTHAK AHMED, P. MUBINA NAZNEEN |
0903-0907 |
Download | |
| IJVDCS 168 | Motion Estimation using A Single Image Analysis Based on Threshold Approach Authors:T. PAVANI, N. M. M. K. PRASAD, K. HYMAVATHI |
0908-0914 |
Download | |
| IJVDCS 169 | Fault Secure Encoder and Decoder Design Orthogonal Latin Squares Codes Authors:B. MEENA, J. LINGAIAH |
0915-0919 |
Download | |
| IJVDCS 170 | Power Saving Topologically-Compressed with 21Transistor’s Flip-Flop using Multi Mode Switches Authors:SURAKALA ANUSHA, MOHANAKRISHNA CHEEDI |
0920-0926 |
Download | |
| IJVDCS 171 | Reduction of Static Power by using Biasing and Body Biasing Techniques Authors:MEESALA SUNEETHA, MOHANAKRISHNA CHEEDI |
0927-0932 |
Download | |
| IJVDCS 172 | Logic Effort of CMOS Based Dual Mode Logic Gates Authors:PUPPALA BHAVANI, DAMERAGIDDE SRINIVAS RAO |
0933-0938 |
Download | |
| IJVDCS 173 | Implementation of High Performance Video Transform Engine by using Reversible Logic Gates Authors:S.JASMINE TAJ, K.GEETHA |
0939-0944 |
Download | |
