Implementation of Aging-Aware Multiplier Design for Area and Power Critical Applications

Authors:BOWRISETTI SPANDANA, G. ASWAN KUMAR

0474-0478

A Study on Implementing Novel Adder in HEVC DCT to Achieve Area And Power Efficiency

Authors:SHANIBA K.K, VEENA K

0479-0481

A Novel Approach to Implement Scalable DCT Architecture for Timing Critical Applications

Authors:MUDIDANA VENKATESH, V. KEERTHI KIRAN

0482-0488

Fault Tolerant Parallel Reconfigurable FIR Filters in VHDL

Authors:NIMMY THOMAS, SUVITHA P. S

0489-0491

VLSI Implementation of Power and Timing Optimized Fixed-Point Circuits

Authors:SETTI JYOTHISREE, B. V. R. GOWRI

0492-0496

Implementation of Low Error And Area Efficient Fixed Width Multiplier by using Minor Input Correction Vector

Authors:RONGALI SIREESHA, P. ASHOK KUMAR

0497-0500

Critical Path- Analysis and Low - Complexity Implementation of the LMS Adaptive Algorithm

Authors:D. SESHAVENI, N. G. N. PRASAD

0501-0505

Power Optimized Implementation of Fault Tolerant Parallel Filters

Authors:SAGIREDDI C S DURGA VARAPRASAD, P.K. SURESH

0506-0510

Implementation of Low Power Resolution Algorithm for Common Sub Expression Elimination in Digital Filter Design

Authors:NAGULAPALLI SURESH, G.V.K.S PRASAD

0511-0514

Low Power Implementation of Data Flow Transformation of Carry Save Representation in Arithmetic Circuits

Authors:MADDIPATI MOUNIKA, T. GANGADHARA RAO

0515-0519