Implementation of 32x32 Modified Vedic Multiplier

Authors:SUGUNA K R, SHAMBHAVI S

0287-0289

Implementation of Real Time Motion Feature Extraction of a Video Sequence on FPGA

Authors:K. V. N. S. TEJU, B. CHANDRA SHEKAR REDDY

0290-0294

A Low Computational Complexity Built-in-Self Test of Transmitter I/Q Mis-match using Self-Mixing Envelope Detector

Authors:THOKALAVIJAYA KANTH, TATIKONDA SRIDEVI

0295-0299

FPGA Implementation of Electro Oculo Gram using Discrete Wavelet Transform

Authors:G. ANANTHA LAKSHMI, K. DEEPTHI

0300-0307

Designing of Low Power and High Speed Modified Carry Select Adder for 16-Bit Vedic Multiplier

Authors:K. KIRAN MURTHY, PADAVALA VEERA SRI DEVI

0308-0312

High Performance Error Detection using Majority Logic Decoder for Memory Applications

Authors:KOTESWARACHARI INKOLLU, T. V. S. ADI NARAYANA

0313-0315

Fully Reused VLSI Architecture of FM0/ Manchester Encoding Using HCPM Technique for DSRC Applications

Authors:M. LAKSHMISHREE, P. BHARATHI, R. GANESAN

0316-0326

A Novel Advanced Common VDD and GND Technique for Low Power CMOS VLSI Design

Authors:AMIT GANGOPADHYAY, NIRBHAY KUMAR

0327-0331

Full Subtractor Design of Energy Efficient, Low Power Dissipation Using GDI Technique

Authors:M. CHAITANYA SRAVANTHI, G. RAJESH

0332-0336

Optimization of Delay and Error Correcting using Fault Tolerant Parallel Filters

Authors:R. VENKATA SUBBAMMA, DR. DOLA SANJAY S

0337-0341