| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 72 | On Line Faults in FIFO Buffers of NOC Routers Authors:JENNE HANUMANTHU, B. MOUNIKA |
0366-0370 |
Download | |
| IJVDCS 73 | Low Noise Amplifier using CMOS Design at Different Frequency Bands: A Review Authors:ADITYA MUDGAL, DR. JANAK B PATEL, NEERAJ GUPTA |
0371-0373 |
Download | |
| IJVDCS 74 | Design and Implementation of Median Filter by using Xilinx Authors:SONTI SAI KUMAR, CH NAVYA DEEPTHI |
0374-0377 |
Download | |
| IJVDCS 75 | Implementation of USB3.0, with Low Power 8B/10B Encoder/Decoder Authors:MADINEEDI KOTESWARAMMA, SK. KHASIM BEE BL |
0378-0381 |
Download | |
| IJVDCS 76 | Design and Implementation of Encoder and Decoder with 3-Bit Ripple Counter Used for High Speed Communication Authors:MAYAKOTI JYOTHSNA, J. DHANYASRI |
0382-0386 |
Download | |
| IJVDCS 77 | High Performance and Lower Power Full Adder Design in Sub Threshold Region Authors:V. RAMA TULASI, P. SUBHASHINI |
0387-0391 |
Download | |
| IJVDCS 78 | Slow-Light-Based Variable Symbol-Rate DQPSK Receiver Authors:MAYAKOTI NAGA CHAMUNDESWARI, SK. KHASIM BEE BL |
0392-0397 |
Download | |
| IJVDCS 79 | Designing A Complex Code for LFSR Random Number Generator Authors:NANDIGAM SATYA SRIDEVI, V. RAMAKRISHNA |
0398-0401 |
Download | |
| IJVDCS 80 | Design Implementation of High Speed PCI using MAC Transmitter with PIPE Interface Authors:DADI SAHITHI, SK.KHASIM BEE BI |
0402-0406 |
Download | |
| IJVDCS 81 | Design of 32-Bit Floating-Point Unit by Reducing Area Power Authors:PENUGONDA VENKATA NAGA PAVANI, SK. KHASIM BEE BL |
0407-0411 |
Download | |
