Design and Implementation of AES Algorithm with UART

Authors:HUMMA NOWSHEEN, B.VASU NAIK

0274-0277

Implementation of Robust Encryption Algorithm for Wireless Communication

Authors:P.PRASANTH, V.SWATHI

0278-0281

Designing of DA Based Adding and Shifting, LUT Based Fir Filters on FPGA

Authors:DHANASHRI KUNTURWAR, M.R.VARGANTWAR

0282-0284

Design of High Speed BCD Adder using LUT

Authors:MALLIREDDY SAI DEEPIKA, M.NARESH BABU

0285-0289

Designing and Compare Analyses of Vedic Multiplier using Compressors and Reversible Logic Gats used Vedic Multiplier

Authors:DASARI SRAVANTHI, B.VASU NAIK

0290-0293

Radix-2k Feed Forward FFT Architectures

Authors:K.KIRAN KUMAR, M.MADHU BABU

0294-0298

Design and Comparison of Effective Area Efficient Architectures for CSLA using CLA

Authors:CH. MANOJ KUMAR, K. MURALI

0299-0304

Design and Simulation of Low Power Approximate Adders using Different Technologies

Authors:U.P. OBULESU, SYAMALA DEVI

0305-0310

Power Reduction of Pulse Triggered Flip Flop using Enhanced Pulse

Authors:P. YASWANTH, KANTE MURALI

0311-0314

Implementation of Self-Calibrated DLL-Based Clock Generator

Authors:REDDIGARI VINEELA, K.CHANDRA SEKHAR

0315-0319