| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 64 | Spartan-6 FPGA Based MEMS Accelerometer Processing Electronics for Navigation Authors:N. LAVANYA, N. ARAVIND |
0332-0336 |
Download | |
| IJVDCS 65 | Design of a Novel High Speed Multiplier by using Gate Diffusion Input Technique Authors:P. NAGARAJU, RAMA KRISHNA NAIK, K. GEETHA, DR. R RAMACHANDRA |
0337-0342 |
Download | |
| IJVDCS 66 | Design of Real-Time Traffic Control System using Verilog Authors:SWETHA, G. SAI PRIYANKA, PRATHYUSHA, MAHESH SHETKAR |
0343-0345 |
Download | |
| IJVDCS 67 | Verification of High Speed and Energy Efficient Carry Skip Adder Authors:I. LAHARI MOUNIKA, J. RAVINDRA |
0346-0349 |
Download | |
| IJVDCS 68 | Implementation of a Novel and Area Efficient VLSI Architecture for Recursion Computation in LTE Turbo Codes Authors:K. SUNEETHA, M. G. BHAVANI, P. KIRANMAI |
0350-0354 |
Download | |
| IJVDCS 69 | An Efficient Method for Multi-Bit Correction using BCH Authors:M. VIJAY KUMAR REDDY, K. BALA |
0355-0357 |
Download | |
| IJVDCS 70 | A Report on Multiplier and Its Types Authors:M. V. S. ASISH, P. S. SINDHU, K. KALKI, D. N. V. BHARATHI |
0358-0361 |
Download | |
| IJVDCS 71 | Design of High Efficient Multiplier using Adaptive Holdlogic Authors:D. SRIDHAR, M. SNEHA BHARATHI |
0362-0365 |
Download | |
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