| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 20 | A Low-Power Single-Phase Clock Multiband Flexible Divider Authors:K. VENKATESWARLU, V. VAMSI MOHANA KRISHNA |
136-140 |
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| IJVDCS 21 | Design and FPGA Implementation of a BPSK Modem on Modern DSP Technology for Wireless Communication Authors:PRABHAKAR.R, VIJAYA BABU.E, SANDHYA.G |
141-148 |
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| IJVDCS 22 | Design and Implementation of a Smart Routing Protocol for Large Supermarkets using WSN Authors:KIRAN KAMATAM, SRI. G. SRIHARI |
149-154 |
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| IJVDCS 23 | A Real Time System for In Home Activity Monitoring of Elders Authors:N. SIVA KUMAR REDDY, K. RADHIKA REDDY |
155-162 |
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| IJVDCS 24 | Joint Design of Automatic Speech Recognition for Speaker and Speaking Environment Authors:RAJU KUMATAM, B. SATISH CHANDRA |
163-169 |
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| IJVDCS 25 | Pixel Bit Manipulation for Data Hiding in an Image Authors:JAWAHER ABDULWAHAB FADHIL, FIRAS FADHI MOHAMMED ABEDI |
170-173 |
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| IJVDCS 26 | Design and Implementation of High Security Mobile Payment System Authors:SRAVAN KUMAR MITTA, M. L. RAVI CHANDRA |
174-184 |
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| IJVDCS 27 | Design and Implementation of Efficient Parallel Prefix Adders on FPGA Authors:M. VENKATA PRAVEEN MANIKANTA, B. SUJATHA |
185-192 |
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| IJVDCS 28 | Low Power and Area Efferent Carry Select Adder Authors:K. PRAKASH, B. ANIL KUMAR |
193-200 |
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| IJVDCS 29 | Deadlock Recovery Technique in Bus Enhanced NOC Architecture Authors:BHUKYA YUGANDHAR, B.MANASA, K. V. VARA PRASAD |
201-208 |
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