| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 40 | .......................................... Authors:........................................... |
.......... |
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| IJVDCS 41 | Efficient Topologically Compressed Transistor Flip-Flop with Power Saving Authors:PULIMI SWETHA, K. SUBHASHINI, K. UPENDRA RAJU |
0222-0227 |
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| IJVDCS 42 | Design of Power Efficient Pulse-Triggered Flip-Flop with Enhancement Scheme Authors:DEVINENI SOWJANYA, S. VENU PRASAD |
0228-0232 |
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| IJVDCS 43 | Implementation of 64-Bit Modified Wallace MAC based on Multi-operand Adders Authors:BALASUBERAHMANYAM DUGGIRELA, YEJJU JYOTHI |
233-236 |
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| IJVDCS 44 | Analysis of Delay, Power and Area for Parallel Prefix Adders Authors:SIKILIGIRI SHAHIN, G. NAVEENA LAKSHMI, K. UPENDRA RAJU |
0237-0240 |
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| IJVDCS 45 | Power Efficient Correlator Design for IEEE 802.16 OFDM Synchronization Authors:SREEKANTH. R, DR. C. R. BYRAREDDY, NARENDRA. C. P |
0241-0245 |
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| IJVDCS 46 | Verilog Implementation of Low Power, High Speed Arithmetic and Logical Unit using 32-Bit Barrel Shifter Authors:RAKSHITH. C, DR. B. G. SHIVALEELAVATHI |
0246-0250 |
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| IJVDCS 47 | BIST Technique for Delay Measurement using Signature Registers Authors:SHIVANAND KUMBAR, SHUBHA B |
0251-0255 |
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| IJVDCS 48 | FPGA Implementation of Reversible Multiplier using K-Algorithm for Image Filtering Application Authors:KAVYA. M, SUNITA SHIRAHATTI |
0256-0261 |
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| IJVDCS 49 | Design and Development of Verification Environment to Verify UART Protocol using UVM Authors:NIRANJAN B S, SUBODH KUMAR PANDA, SHANTHI V A |
0262-0264 |
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