Implementation of High Throughput Truncated Multiplier

Authors:B. HEMA LATHA, D. GOPI

0268-0271

Performance Evaluation and Implementation of Parallel Multipliers

Authors:MANASWINI ADHIKARI, RAJESH KUMAR MISHRA, SANDIPAN PINE

0272-0278

VLSI Architecture of High Performance Frequency Multiplier for DLL Clock Generator

Authors:RAVURI HANUMANTHA RAO, V. VIJAYA MONICASINDHU

0279-0283

Implementation of Carry-Skip Adder Under A Wide Range of Supply Voltage Levels for High-Speed and Energy Efficient Applications

Authors:VENKATA UDAY KUMAR MADDIKUNTLA, HANUMANTA RAO

0284-0289

Realization of Advanced Encryption Standard for Safety Communication Using Verilog

Authors:SREEVALLI GUTTI, R. SUNIL

0290-0293

Ultra-Low Power VLSI Designs using Adiabatic Logic in Sub Threshold Region

Authors:D. RAMESH CHAND, HANUMANTA RAO

0294-0299

Efficient Design of Testable Reversible Circuits using Verilog HDL

Authors:TAMMISETTI ASHOK, K. V. PRAVEEN

0300-0304

A Very High Speed AES Implementation for 100Gbps Communication Links

Authors:U. SAI PRAKASH, M. HARI KRISHNA, S. NAGI REDDY

0305-0309

Low Power And Efficient Design of SPST for Multimjedia Applications Using Verilog HDL

Authors:BALUGURI SAKUNTHALA, S. BHAVANI

0310-0313

Design of a Processor by Reducing Instructions using Advance Verilog Methods

Authors:SYED AZHAR

0314-0317