Submission Open for Jan-Dec-2024 |
Last Date of Submission : |
20th, April-2024 |
Acceptance Notification : |
After Peer Review |
Last Date of Publication : |
30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
S.NO | TITLE | PAGE NO | DOWNLOAD | |
IJVDCS 17 | An ASIC Implementation of Automated Teller Machine Controller for Secured Financial Transactions Authors:PONNA. DIVYA, AMMIREDDY LAVANYA, TADI. CHANDRA SEKHAR |
0112-0120 |
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IJVDCS 18 | A Novel Approach of Power Reduced TPG for BIST Controller Authors:LAXMI PRASAD CHEGURI, K.PRABHAKARA RAO |
0121-0128 |
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IJVDCS 19 | An Intelligent 4-Lane Density based Traffic Light Control System Authors:TANUKU YEJASWINI, AMMIREDDY LAVANYA, TADI. CHANDRA SEKHAR |
0129-0133 |
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IJVDCS 20 | A Low Power Implementation of RCEAT for RFID in Wireless Systems Authors:A.SUDARSINI, B.P.V.V.B.NARASIMHA RAO, TADI. CHANDRA SEKHAR |
0134-0140 |
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IJVDCS 21 | Communication between Two FPGA Systems using RTOS and Microblaze Authors:MANDADA VINUSH, VIDATALA RAGHAVENDRA |
0141-0146 |
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IJVDCS 22 | Implementation of Low Power Memories by 8T SRAM based on Column Decoupled Logic Design Authors:T.KEERTHI PRIYA, SUMITHA.H, K.PRASANTH |
0147-0153 |
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IJVDCS 23 | Image Enhancement Based on Super Resolution with Interpolation Methods using Multi-Surface Fitting Authors:F.ASMA BEGUM, NAZIA SHABANA, NAHID JABEEN |
0154-0160 |
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IJVDCS 24 | Low Power and Reduced Latency Implementation for Parallel Prefix Adders Authors:P.NOOKARAJU, D.POTHU RAJU |
0161-0166 |
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