| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 30 | Realization of Power Optimized OCP Bus Architecture for Network On-Chip Applications Authors:M.ANIL KUMAR, K.SIRISHA |
0164-0170 |
Download | |
| IJVDCS 31 | Comparison of CMOS and CNFET Based Op-Amp Authors:AAKIL BAPNA, PRASHANT MANI |
0171-0174 |
Download | |
| IJVDCS 32 | Implementation of PUF on FPGA Authors:C.PALLAVI1, K.MOUNIKA, T.NARENDRA BABU, M.RAGHUPATHY |
0175-0179 |
Download | |
| IJVDCS 33 | Realization of Security-Enabled Flexible Architecture with Symmetric Cryptography Authors:R. DEEKSHITHA, S. T. MRUDULA |
0180-0184 |
Download | |
| IJVDCS 34 | Implementation of FIR Truncated Filter Based on Low Power and Memory Reduction Analysis Authors:YELLIPOGULA MALLIKARJUNA, VADTHYA RAVINAIK |
0185-0191 |
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| IJVDCS 35 | FPGA Implementation of Advanced Encryption Standard Algorithm Authors:APARNA AMBULE, DR.Y.V.CHAVAN |
0192-0196 |
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| IJVDCS 36 | A New Reducible Complexity Hardware Efficient FIR Filter by using Proposed Shift and Adder Architectures Authors:CH. GOVERDHAN REDDY, B. SANTOSH KUMAR, K. SRINIVASULU |
0197-0201 |
Download | |
| IJVDCS 37 | Design and Implementation of Multi Operand Redundant Adders for FPGAs Authors:P. SANTHOSH, SOUJANYA, K. SRINIVASULU |
0202-0207 |
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| IJVDCS 38 | Review on: Major Barriers of FinFET Scaling Authors:KINJAL M. AMIN, BHAVESH H. SONI |
0208-0211 |
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| IJVDCS 39 | A Novel VLSI Architecture for Image Compression Through Spurious Power Suppression Technique Authors:AISHWARYA A S, ANITHA P |
0212-0216 |
Download | |
