Submission Open for Jan-Dec-2024 |
Last Date of Submission : |
20th, April-2024 |
Acceptance Notification : |
After Peer Review |
Last Date of Publication : |
30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
S.NO | TITLE | PAGE NO | DOWNLOAD | |
IJVDCS 212 | A Novel Digital Sub Threshold Logic for Ultra-Low Power Condition Authors:SYEDA MUSHARRAF TASKEEN, G. JHANVI, R. PRIYANKA |
1130-1136 |
Download | |
IJVDCS 213 | Reconfigurable BISR Scheme with ECC Based Repairable RAMs for Reliable SOC Design Authors:SRINIVAS K, DIVYA KANUGANTI |
1137-1144 |
Download | |
IJVDCS 214 | Design And Development of Fast Switching Devices for Ultra Low Power Applications using TFET Authors:P. NIRMALA, DR. G. V. MAHA LAKSHMI |
1145-1151 |
Download | |
IJVDCS 215 | Implementation of High Speed And Low Complexity Effective Version of Montgomerys Algorithm Authors:PUPPALA S S S N DILEEPKUMAR, CHIKKIREDDY VEERA MALLIKARJUNA |
1152-1156 |
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IJVDCS 216 | An Optimized Fault Tolerant Parallel Filters Based On Error Correction Codes using Reversible Gates Authors:VENNETI. KUMAR RAJA, TUMMURI.V.V.PURNA CHANDRA SEKHAR |
1157-1161 |
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IJVDCS 217 | A Fixed Point Implementation of Expanded Audio CORDIC Algorithm Authors:PALA LAVANYA DEVI, TUMMURI.V.V.PURNA CHANDRA SEKHAR |
1162-1168 |
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IJVDCS 218 | A New 3T Gain Cell EDRAM for Low Power Application Authors:NAVEEN KUMAR GANJALA, V. V. MONICA SINDHU, K. VIJAYA PRASAD |
1169-1173 |
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IJVDCS 219 | Design of High Speed DDR3 SDRAM Controller Authors:NETHAGANI KAMALAKAR, G. RAMESH |
1174-1178 |
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IJVDCS 220 | A Novel Trade-offs for Threshold Implementations Illustrated on AES Authors:PRATHIPATI KAVITHA, S. BHAVANI, K. VIJAYA PRASAD |
1179-1185 |
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IJVDCS 221 | Design of RF Transceiver in Wireless Sensor Networks Authors:BUSHIPAKA MADHUKAR, CHAND PASHA MOHAMMED, B. MADHUSUDHAN REDDY |
1186-1190 |
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