| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 239 | Low-Power and Area-Efficient Shift Register using Pulsed Latches Authors:G.SAMPOORNA, D.CHANDRA PRAKASH |
1239-1243 |
Download | |
| IJVDCS 240 | An Advanced Architecture for 16-Bit Polar Codes using Partially Parallel Encoder Authors:SHANIGARAPU MOUNIKA, P.VENKATESHWARLU |
1244-1246 |
Download | |
| IJVDCS 241 | Design and Implementation of MAC Protocol for Full-Duplex Wi-fi Networks Authors:P.YASWANTH, P.RAVINDRABABU, AYESHA TARRANUM |
1247-1255 |
Download | |
| IJVDCS 242 | Designing of Hybrid Ring Oscillator Physical Unclonable Function for Lightweight Applications Authors:BADDALA NAGAMANI, P.PADMAJA |
1256-1261 |
Download | |
| IJVDCS 243 | FM0 and Manchester Encoding in Single Architecture Design by SOLS Technique for DSRC Applications Authors:KANDUKURI SUNITHA, N. SRINIVAS |
1262-1266 |
Download | |
| IJVDCS 244 | Low-Complexity Tree Architecture for Finding the First Two Minima Authors:LINGALA SRI LAXMI PRASANNA, YADALA RAVINDRA |
1267-1270 |
Download | |
| IJVDCS 245 | Efficient Area And Power Utilization of Shift Register using Pulsed Latches Authors:MOHAMMED YASMEEN, A. ARUN KUMAR |
1271-1276 |
Download | |
| IJVDCS 246 | Design and Implementation of a Novel Low Power Digital OTA Authors:G. SWAMY, SANA RANJITHA |
1277-1280 |
Download | |
| IJVDCS 247 | Design of 14-Transistor Hybrid Full Adder with Full Swing Node Voltages Authors:JAKKULAMADHAVI, KOLLIPARARAMYAKRISHNA |
1281-1284 |
Download | |
| IJVDCS 248 | Design of FINFET Based Schmitt Trigger using Variable Body Biasing Technique Authors:M. UDAY KUMAR, AVULA GANESH, B. YESU VBCE |
1285-1288 |
Download | |
