Implementation of a Design Synthesis for Evaluation of FPGA Designs with Mixed LUTs for Area Efficiency

Authors:SAMIYA AFROZE, G. ARUNA

1043-1046

An Efficient Multiplier Design using Carry Skip Adder Operating Under A Wide Range of Supply Voltages Levels for High Speed & Low Power Appliance

Authors:ZAKIA FATIMA, K. PREMA LATHA

1047-1053

Area And Power Efficient of PreEncoded Multipliers using NR4SD

Authors:E. BALA KRISHNA, TADIMARI RESHMA

1054-1058

Design of Hybrid CA LFSR Based BIST Enabled UART

Authors:CH. ANUDEEP, S. K. SATHYANARAYANA

1059-1062

Design and Implementation of Reverse Multiplier using Approximate Compressor

Authors:PENNAMAREDDY ASHOK, A. CHANDRABABU

1063-1068

FPGA Implementation of Filtered Image using 2D Gaussian Filter

Authors:GORATI SAI THIRUMAL, P. SHANKAR, VADTHYAVATH VIJAYA

1069-1075

Hardwae Secuity Challenge Beyond CMOS:Attacks and Remediez

Authors:VADTHYAVATH VIJAYA, P. SHANKAR, GORATI SAI THIRUMAL

1076-1081

High Throughput Finite Field Multipliers using Redundant Basic for FPGA Implementation

Authors:S. PRASAD, CH. SATHYANARAYANA

1082-1086

Real-time Implementation of the ViBe Foreground Object Segmentation Algorithm

Authors:P. SHANKAR, GORATI SAI THIRUMAL, N. DASHARATH

1087-1091

A Humble Theory and Application for Logic Encryption

Authors:P. SHANKAR, GORATI SAI THIRUMAL, VADTHYAVATH VIJAYA

1092-1101