Submission Open for Jan-Dec-2024 |
Last Date of Submission : |
20th, April-2024 |
Acceptance Notification : |
After Peer Review |
Last Date of Publication : |
30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
S.NO | TITLE | PAGE NO | DOWNLOAD | |
IJVDCS 228 | Reduce Area Delay Architecture of FIR Digital Filter using Distribution Arithmetic Authors:AKAM ANUSHA, D.VEERANNA |
1176-1182 |
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IJVDCS 229 | Parity Preserving Adder/Subtractor using a Novel Reversible Gate Authors:B.MOHAN, J. LINGAIAH, M.RAVI TEJA |
1183-1186 |
Download | |
IJVDCS 230 | Low-Power and Area-Efficient Shift Register using Pulsed Latches Authors:K. SWATHI, JADA LINGAIAH |
1187-1191 |
Download | |
IJVDCS 231 | Design of Power Optimal Reversible FIR Filter for Speech Signal Processing Authors:KOMMU NARESH, P RAHUL REDDY |
1192-1198 |
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IJVDCS 232 | Smart Robot for Industrial Applications Authors:MEENA, SRI LAKSHMI |
1199-1204 |
Download | |
IJVDCS 233 | BIST Design with Test Pattern Monitoring for SoC/NoC System Authors:PARUPALLY KEERTHI, AYESHA TARRANUM, O.NAVAJEEVANRAJU |
1205-1209 |
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IJVDCS 234 | Designing of Shift Register by Pulsed Latches for Reducing Power Authors:KARNATI SHARMILA, AYESHA TARRANUM |
1210-1214 |
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IJVDCS 235 | www.ijvdcs.org Copyright @ 2016 IJVDCS. All rights reserved. VLSI Design of a High Speed and Area Efficient Multiple Constant Multiplications (MCM) using Modified Booth Algorithm Authors:T. NIKHIL TEJA, M. MADHUSUDHAN REDDY |
1215-1221 |
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IJVDCS 236 | Design and Implementation of Vedic Sutras for Square and Cube Architecture on FPGA Authors:SHEIK GOUSE PASHA, AYESHA TARRANUM |
1222-1225 |
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IJVDCS 237 | Designing of Clock – Tree Architecture for Mixing Drivers Authors:MALOTHU CHANDRA SHEKHAR NAIK, N.VEERAIAH, AYESHA TARRANUM |
1226-1229 |
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