FPGA Implementation of a Image Encryption System using AES Algorithm

Authors:DR. G.V.R.SAGAR, G.ASHOK KUMAR

1129-1133

Area Efficient, Power Efficient ALU Design using Modified Gate Diffusion Input

Authors:DUPATI ANIL, AVULA GANESH

1134-1137

Transistor-Level Optimization of Three Input XOR/XNOR Gate Using CMOS Logic Design

Authors:G. GOPAL, B. PAPA CHARY

1138-1145

Design and Simulation of Power Efficient Pulse Triggered Flip-Flop

Authors:KUSUMA NAGARAJU, AVULA GANESH

1146-1148

A 32-Bit Multiplier Implementation using Modified Booth Algorithm

Authors:N. HEMANTH GOWTHAM KUMAR, KUPPAM N CHANDRASEKHAR, K. BALACHANDRA

1149-1152

Designing of Fast and Low Complexity Tree Architecture for Finding Minima Values in LPDC System

Authors:T. MANI DEEPTHI, N. VEERAIAH, AYESHA TARRANUM

1153-1156

Design and Implementation of Finite Fielded Multipliers for Cryptography Process on FPGA

Authors:KURAKULA MOUNIKA, AYESHA TARRANUM, N. VEERAIAH

1157-1162

Designing of Pulse Triggered Flip-Flop with Low Power and Area Efficient By Using Conditional Pulse Enhancement Scheme

Authors:N. RAVALI, KOTA VENKATESWARA RAO, O. NAVAJEEVANRAJU

1163-1168

Real Time Noise Suppression in Images by using Efficient Median Filter Technique

Authors:UPENDRA RAVADA, DONTABHAKTUNI JAYAKUMAR, Y. DAVID SOLOMON RAJU

1169-1172

Optimization of Full Subtractor Circuit using Gate Diffusion Input Methodology

Authors:SUMAN SHARMA, AVULA GANESH

1173-1175