Low Power and High Speed Implementation of 1-Bit Hybrid Full Adder using GDI Techniques

Authors:MANDAPATI DURGADEVI, CH.SRIGIRI

0886-0890

Design and Implementation of Pulsed Latch Based Shift Register Using Body Biasing Techniques

Authors:BUDDIGA PRIYANKA, CH.SRIGIRI

0891-0894

Performance analysis of DEM Circuits with DTCMOS Techniques Using PTM45nm Technology

Authors:YANDAPALLI VEERABABU, KILARI JYOTHI

0895-0897

Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology

Authors:S. SARATH CHAND1, KUPPAM N CHANDRASEKHAR, K.BALACHANDRAR

0898-0902

Removal of Impulse Noise in Images using Adaptive Decision Tree Based Image Denoising

Authors:S. VAISHNAVI, G. SRIDEVI

0903-0910

Detecting and Correcting Multiple Bit Upsets using Erasure Codes for Protecting SRAM Based FPGAs

Authors:D. GNANENDRA REDDY, K. PURNACHANDRA RAO, DR.V.THRIMURTHULU3=

0911-0916

Implementation of D-Latch Based CSLA for Speed Critical Application

Authors:BIJJA REKHA, D.SAILAJA

0917-0920

Implementation of Brent-Kung Adder Using QCA Technology

Authors:MALOTHU KIRAN KUMAR, CH.CURY

0921-0926

Evaluation of Truncated Multiplier for High Speed and Low Power Applications

Authors:E.ASHOK, D.SAILAJA

0927-0930

VLSI Computational Architectures for the Arithmetic Cosine Transform

Authors:D. DIVYASRI, N.ASHOK KUMAR, G.CHANDRASHEKAR REDDY

0931-0936