Design Optimal Transistor Network Full Adder by using Graph Based Method

Authors:N.MANASA, T.KEERTHI PRIYA, K.PRASANTH

0937-0939

Hardware Implementation of Image Denoise Filters using System Generator on ZYNQ Board

Authors:V.HANISHA, G.VIMALA KUMARI

0940-0946

Implementation of Testable Reversible Sequential Circuit on FPGA

Authors:K. SHRAVYALA, D.CHANDRA PRAKASH

0947-0951

Low-Power Pulse-Triggered Flip-Flop Design Based On A Signal Feed-Through Scheme

Authors:PEETHALA MOUNIKA, PAPANI. SRINIVAS, M.S. RAJESWARI, RAJAIAH GABBETA

0952-0957

Reliable Low-Power Multiplier Design using Fixed-Width Replica Redundancy Block

Authors:K.SRUTHI, M.S. RAJESWARI, RAJAIAH GABBETA

0958-0962

SRAM Cells using Test Vector Monitoring in BIST Architecture for SOC

Authors:BALEM SINDHUJA, PAPANI SRINIVAS, M.S RAJESWARI, RAJAIAH GABBETA

0963-0967

Design of A Nonvolatile 7TIRSRAM Cell for Instant On Operation

Authors:DORNALA NAVYA, G.RAJAIAH, M.S RAJESWARI

0968-0974

Digital Comparator Design for High Speed Binary Comparison

Authors:D. JOHARI KISHAN, K.KEERTHAN, G.RAJAIAH

0975-0978

Antifuse Algorithm on Ring Oscillator on Bi-Directional Counter Temperature

Authors:SHAIK SHAFI HUSSAIN, Y. PRAVEEN KUMAR REDDY

0979-0982

Hybrid Variable High Performance Carry Skip Adder Structure

Authors:TUPAKULA MADHURI, K. KAMESWAR REDDY

0983-0985