Design and Implementation of Testable Reversible Sequential Circuits for Fault Coverage

Authors:KOTRA SWATHI, M .VINAY KUMAR

1013-1018

High-Performance VLSI Architecture for AES-GCM Algorithm with Sub Pipelining

Authors:B. LOHITHA, K. PADMA VASAVI

1019-1024

32-Bit Unsigned Multiplier Designed by CSLA, CLAA, CBLA Adders

Authors:A. SWAPNA, K.THIRUPATHI

1025-1029

High Speed Arithmetic Operations using Quaternary Signed Digit Number System

Authors:T.RAMANJUL REDDY, C. VISHNU VADRHAN REDDY

1030-1034

Implementation of Power Optimized Fault Coverage Circuit Design for Testing Applications

Authors:KAVURI SUNEETHA, J.I.R.PRAKASH

1035-1039

Evaluation of Sparse Tree RSFQ Adder for High Speed Applications

Authors:KURRA VIJAY KUMAR, M.SUMALATHA

1040-1044

Implementation of Dual Dynamic Node Pulsed Hybrid Flip-Flop Using Low Power Techniques

Authors:P. SIRISHA

1045-1051

Fault Detection in Majority Logic Decoder of EG-LDPC Codes to Reducing Access Time for Memory Applications

Authors:T. KIRAN KUMAR, K. THIRUMALESH

1052-1057

Speed Optimized Realization of Reversible Vedic Multiplier using Urdhva Tiryakbhayam Sutra

Authors:AKKI SIVA KRISHNA YADAV, N. SURESH BABU

1058-1063

Implementation of Adaptive Biased Operational Amplifier with Improved Slew-Rate

Authors:CH.VIKAS, F.K. PAVAN KUMAR

1064-1068