| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 1 | Implementation of High Speed NoC Router with Data Encoding Techniques Authors:RAJANI CHERUKURI, K. PRADEEP |
001-003 |
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| IJVDCS 2 | An Optimizing Area And Power To Minimizing Functional Constraints Using Low Power-Linear Feedback Shift Register Authors:PERICHERLA LAKSHMI SINDHUJA, S. MALLIKA MATTAPARTHI, A. V. S. S. VARMA, GANCHI SAMPATHLAL |
004-007 |
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| IJVDCS 3 | An Optimized Power and High Speed Functional Broadside Tests using BIST Authors:APPIKONDA LEELA LAKSHMI, BIGHNESWAR PANDA |
008-014 |
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| IJVDCS 4 | Design of Area Efficient 64-Bit MDC FFT Processor Authors:GANDI ALEKHYA DEVI, NANCHARAIAH VEJENDLA |
015-019 |
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| IJVDCS 5 | High Performance and Area Efficient Flexible DSP Datapath using LP Gates Authors:GARIMELLA SAI JYOTHI, M. J. R. M. PRASAD |
020-024 |
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| IJVDCS 6 | Implementation of UART Based Testable Circuits using Reversible Logic Authors:JAYANTHI SRINIVAS RAVI KANTH, ASHOK KUMAR PENTA |
025-031 |
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| IJVDCS 7 | VLSI Realization of Data Encoding Techniques Based High Speed NOC Router Authors:PILLUTLA THANUJA, P. SATEESH KUMAR |
032-034 |
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| IJVDCS 8 | High Throughput Implementation of 64-Bit MAC Multioperand Adders Authors:K. H. SANTHOSHI KUMARI, VALIVETI RAVI TEJESVI |
035-037 |
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| IJVDCS 9 | High-Speed and Energy-Efficient Carry Skip Adder Operating Under A Wide Range of Supply Voltage Levels Authors:YALLAMPALLI RAJESWARI DEVI, M. K. CHANDRASEN |
038-041 |
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| IJVDCS 10 | An Optimized Power Bist Based On Mask Pattern Generation Using LP-LSSR Authors:AVANTHI MALLA, B. SANGEETH KUMAR |
042-048 |
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