Submission Open for Jan-Dec-2024 |
Last Date of Submission : |
20th, April-2024 |
Acceptance Notification : |
After Peer Review |
Last Date of Publication : |
30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
S.NO | TITLE | PAGE NO | DOWNLOAD | |
IJVDCS 1 | Efficient Power Delay Product Realization of Montgomery Multiplier Based on Pentanomials Authors:VELLANKI JAGANNADHA RAO, M. SRIHARI |
0001-0004 |
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IJVDCS 2 | Design & Implementation of VGA Display System Based on CPLD and Dual Memory Authors:G. SRAVANTHI, DR. M. GURUNADHA BABU |
0005-0009 |
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IJVDCS 3 | Design of Area Optimized Spanning Tree Adder using Quaternary Logic Authors:ERUDI VENKATA PUSHPA LATHA, M.SATEESH BABU |
0010-0017 |
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IJVDCS 4 | Power Optimized Realization of On Chip Network using OCP Protocol Authors:SANDHYA KUMARI PYLA, A.JAYA VANI |
0018-0024 |
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IJVDCS 5 | Implementation of Motion Estimation Testing Applications Based On Error Detection and Data Recovery Architecture Authors:M. RAKESH GOUD, P.SIREESHA |
0025-0030 |
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IJVDCS 6 | Designing of Low Power ECRL Based Fine-Grain Power-Gated Logic for Asynchronous Circuit Authors:P. SUNITHA, K. SANTOSH KUMAR |
0031-0037 |
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IJVDCS 7 | Realization of Multiplexer Based Digital Comparator for Low Power Applications Authors:LOLABHATTU H S ESWARI, M. SATEESH BABU |
0038-0042 |
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IJVDCS 8 | Low Leakage and Ground Bounce Noise Reduction for Sleep Transistor Based CMOS Design in Submicron Technologies Authors:CH. NAVEEN KUMAR, DR.S.BALAJI |
0043-0049 |
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IJVDCS 9 | A VLSI Based Design of Reduced Power On-Chip Coarse-Grained Network Processor Authors:MELLAM USHA RANI, R.SATHYA VENI |
0050-0053 |
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IJVDCS 10 | Implementation of Hold Enabled BIST Controller for Fault Detection in Circuits Implemented on FPGA Authors:G.TRINATH, G.PRASAD ACHARYA |
0054-0058 |
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