| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 71 | CT Based Multimodal Medical Image Fusion Through Multi-Feature Set Analysis Authors:PURUSHOTHAM, H. DEVANNA, T. CHAKRAPANI, K. SUDHAKAR |
362-365 |
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| IJVDCS 72 | A Novel Feature Extraction Technique for Human Action Recognition from Video Databases Authors:REVATHI, M. CHENNAIAH, T. CHAKRAPANI, K. SUDHAKAR |
366-368 |
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| IJVDCS 73 | Design and Implementation of Low Power BIST Using for LFSR Authors:M. REVATHI, N. VAMSI PRAVEEN |
369-372 |
Download | |
| IJVDCS 74 | Implementation of Reversible Sequential Circuits Optimizing Quantum Cost, Delay Outputs Authors:MACHAVARAPU NAGA RAVINDRA, GHANCHI SAMPATHLAL |
373-379 |
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| IJVDCS 75 | Implementation of Reducing the Computation Delay in Radix-16 Booth Multipliers Authors:PEYYILA RAJESH, GUNJA VIJAYARAJU |
380-385 |
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| IJVDCS 76 | Physical Design Implementation of Torpedo Sub System Authors:S. JEEVAN SAI, P. V. J. RAJ KUMAR |
386-390 |
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| IJVDCS 77 | Implementation of Power Optimized Error Correction Based Parallel Filters Authors:GUDUPU MOUNIKA, E. MANEMMA |
391-395 |
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| IJVDCS 78 | Implementation of Power Optimized FFT based on Wallace Multiplier Authors:S. A. DURGA DEVI, B. V. V. SATYANARAYANA |
396-400 |
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| IJVDCS 79 | Realization of Optimised Wallace Multiplier based FFT Architecture Authors:VENKATA LAKSHMI R, V. NANCHARAIAH |
401-405 |
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| IJVDCS 80 | Implementation of Power Optimized FIR Filter Architecture Authors:A. SWETHA, V. NANCHARAIAH |
406-410 |
Download | |
