| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 61 | Implementing A Full Adder/ Full Subtractor Using Parity Conserving Reversible Gates Authors:Y. LAHARI, K. VENKATESH, P. PAVITHRA, S. SIREESHA, P. NAGARAJU |
309-315 |
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| IJVDCS 62 | Secured Electronic Voting Machine by using Biometric Authors:CH. VENKATESWARLU, G. MOUNIKA, M. SRAVANI, B. RAJITHA, SK. SHAMEULLA |
316-319 |
Download | |
| IJVDCS 63 | Design of High Speed Reconfigurable Cordic Authors:P. GOWTHAMI, K. VIJAYA PRASAD |
320-323 |
Download | |
| IJVDCS 64 | Design And Analysis of Approximate Floating-Point Adders Authors:V. JYOTHSNA, S. BHAVANI, K. VIJAYA PRASAD |
324-330 |
Download | |
| IJVDCS 65 | Highly Efficient Decoder Architecture for Polar Codes Authors:M.VINODE KUMAR, R.SUNIL, K. VIJAYA PRASAD |
331-335 |
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| IJVDCS 66 | A Modified Partial Product Generator for Redundant Binary Multipliers Authors:G. SRUJANA, G. ANUSHA, K. VIJAYA PRASAD |
336-340 |
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| IJVDCS 67 | Arithmetic Algorithms for Higher Precision using Floating-Point Expansions Authors:K.VENKATA ANUSHA, P. NAGA SRIKANTH, K. VIJAYA PRASAD |
341-344 |
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| IJVDCS 68 | Design of Error Free Parallel FFTs using Error Correction Codes And Parseval Checks Authors:U. KRUPA, A. NAGA HIMAJA, K. VIJAYA PRASAD |
345-349 |
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| IJVDCS 69 | Design of Hybrid LUT/Multiplexer for CLB Blocks In Fpga Logic Architectures Authors:B.VANAJA, M.VAISHNAVI, K. VIJAYA PRASAD |
350-355 |
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| IJVDCS 70 | Memory-Reduced Turbo Decoding Architecture Authors:B. RAVI KIRAN, K. VIJAYA PRASAD |
356-361 |
Download | |
