Efficient Cut-set Retiming Approach for Fixed Point Circuits

Authors:YERUBANDI BHARGAVA DIVYA, NIMMAKAYALA RAMYA SRI DEVI RESHMA, GOLUGURI VARALAKSHMI, TATA KAMESWARA SURYA TEJA, CHODAPANEEDI SAI KIRAN, GHANCHI SAMPATH LAL

212-217

An Efficient Design of Multi Operand Redundant Adders using Compressors

Authors:FAYAZ BASHA SHAIK, K. NIRANJAN KUMAR

218-225

Implementation of Area Efficient Carry-Select Adder

Authors:K. RENUKA PRIYADARSHINI, V. NARAYANA REDDY

226-231

Design and Analysis of Low Power Static RAM Cell

Authors:AKASH KUMAR GUPTA, P. SHARON RAJU, M. JAIDEEP BHAGAVAN, ANIL KARIMIREDDI, K. RAJESH

232-235

An Efficient Threshold Logic Design for Delay Optimization

Authors:B. S. S. V. RAMESH BABU, D. HARIKA, P. SWATHI, B. SAI KIRAN, M. AKHIL

236-240

Design And Implementation of Efficient Flip-Flops using Transmission Gate Logic

Authors:M. DIVYA, B. KOMALA, J. K. L. PRASANNA, N. S. SUMANTH, P. JASWANTH

241-244

An Efficient Schmitt Trigger SRAM Circuit For Better Access Time And Better SNM

Authors:M. PAVAN KUMAR, B. GOWTHAMI, P. LAKSHMI CHETANA, K. JAGADEESH KUMAR, CH. BHARGAV

245-247

An Efficient Level Converter Model for Power Optimization

Authors:M. PAVAN KUMAR, V. SASIKALA, P. PRASANTH, P. PADMAJA, V. MUKUNDA RAJU

248-252

Implementation of An Efficient High Speed Wallace Tree Multiplier

Authors:A. SAI RAMYA, P. SAKETH BHARADWAJ, V. HARSHITA MEHERA, J. OJASWITHA SUNANDHINI, Y. YASHWANTH

253-256

An Optimized Implementation of Vedic Multiplier

Authors:SIRISHA A, MOHAN KALYANI D, KUMAR SWAMY A, ASWINI D, DHARMA RAO A

257-260