| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 31 | High Performance Voltage Multiplier using Gated Voltage Level Translator Authors:G. RAJESWARI, K. ANUSHA, K. VIJAYA PRASAD |
142-145 |
Download | |
| IJVDCS 32 | High Speed And Low Power Approximate 16-Bit Adder Authors:T. RENUKA, J. SUMALATHA, K. VIJAYA PRASAD |
146-152 |
Download | |
| IJVDCS 33 | Design of Parallel Prefix Adder using Less Critical Path For High Speed Applications Authors:M. SAI KRISHNA, R. SUNIL, K. VIJAYA PRASAD |
153-156 |
Download | |
| IJVDCS 34 | Design of Signal Nodes Upsets Tolerant in 10T Memory Cell Authors:CH. SARITA, K. VIJAYA PRASAD |
157-161 |
Download | |
| IJVDCS 35 | Design of Adder And Subtractor using Reversible Logic Gates Authors:P. NAGA TARUN, T. DEVA KUMAR, K. VIJAYA PRASAD |
162-165 |
Download | |
| IJVDCS 36 | High Speed Low Power Approximate Compressor for Multiplication Authors:M. VENU, R. SUNIL, K. VIJAYA PRASAD |
166-170 |
Download | |
| IJVDCS 37 | Design of efficient Area and Power VLSI Architecture for TCAM Authors:KS. SHAMA FIRDOUS, R. HARITHA |
171-175 |
Download | |
| IJVDCS 38 | A New Approach of Area And Power Radiant Dadda Multiplier by using 8:2 Compressor Authors:GAGGUTURU EASUB, BOMMA LOKESWAR REDDY |
176-179 |
Download | |
| IJVDCS 39 | Modified Adder for Approximate Computing using Masking Technique Authors:SUDDALA AMARNATH, S. SHASHIKUMAR |
180-183 |
Download | |
| IJVDCS 40 | Novel Approach for High Speed AES by CMAC Authors:CHALAMKOTA HEMANANDINI, S. SHASHI KUMAR |
184-189 |
Download | |
