| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Volume1 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 21 | Design of a Parallel Self Timed Adder using Reversible Logic Gates Authors:I. MANOGNA, PREETHI, DR. S. BALAJI |
0102-0107 |
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| IJVDCS 22 | ijvdcs.org Copyright @ 2017 IJVDCS. All rights reserved. Design and Implementation of Arithmetic Cosine Transform Using Vedic Mathematics Authors:K. SRINIVASA REDDY, PRASAD JANGA, S. GOPALA KRISHNA |
0108-0115 |
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| IJVDCS 23 | Area Efficient Architecture for Finding the First Two Minima Authors:E. SWATHI, SHOBHA RANI, R. ANUSHA |
0116-0120 |
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| IJVDCS 24 | A Novel Cryptography using Attribute Techniqe Authors:Y. MOUNIKA, C. SANTHI, DR. M. GURUNADAHA BABU |
0121-0124 |
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| IJVDCS 25 | Design of Full Order Circuit using Double Gate Mosfet Authors:R. GANESH, D. CHANDRA PRAKASH |
0125-0130 |
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| IJVDCS 26 | Implementation of Power Optimized BIST Architecture Authors:G.SATISH KUMAR, N.G.N. PRASAD |
0131-0137 |
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| IJVDCS 27 | Functional Implementation of Area Efficient Asynchronous Full Adder CMOS Architecture Authors:YADLA SRAVAN KUMAR, ANURADHA R |
0138-0143 |
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| IJVDCS 28 | An Efficient Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding Authors:K. MOHAN, G. NAGARAJU, J. HANUMANTHU |
0144-0148 |
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| IJVDCS 29 | Reused Architecture of FM0/Manchester Encoding using SOLS Technician for DSRC Applications Authors:C. PAVANI, K. REMYA |
0149-0155 |
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| Prev | 3 |
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