Delay Efficient Implementation of Shift Registers by using Pulsed Latches

Authors:OBULA HARIKA, K. MONICA, K. PRADEEP KUMAR

559-564

Implementation of Data Encoded Network Interface Router for Power Optimized Applications

Authors:VANKIREDDI PAVANI, D. DHANASEKHAR, K. PRADEEP KUMAR

565-570

A Novel Secure Image Technique for Mosaic Images Transmission using Reversible Color Transformations

Authors:BHARATHI P, A. M. SHAFEEULLA, K. PRADEEP KUMAR

571-577

Joint Statistical Modeling based Image Restoration in a Space-Transform Domain

Authors:PASUPULA BINDU, K. BALA MURALI, K. PRADEEP KUMAR

578-563

Design and Implementation of FIR Filter Architecture for Fixed and Reconfigurable DSP Applications

Authors:S. RAJESH, N. SUBBARAO

564-568

Implementation of Area And Delay A New Finite Field Multiplier Using Error Correction Code

Authors:M. MOHAN, K. BALA CHANDRA

569-573

Implementation of Area And Delay Modified Reversible Adders for Efficient Design of The Add-Multiply Operator

Authors:CHAVALA SRUTHI, S. EKBAL ALI

574-578

Implementation of Skip Techniques for High-Speed Carry-Propogation in D-LATCH

Authors:P. STEEVENSON, M. P. CHENNAIAH

579-582

A Generalized Algorithm and Efficient Architecture for Mixed-Decimation MDF Structure for Radix-2 K Parallel FFT

Authors:B. SATISH BABU, N. SUBBARAO

583-590

Realization of Carry Speculative Adder for Low Power Applications

Authors:CHEJARLA MASTHANAIAH, M. P. CHENNAIAH

591-595