Input Vector Monitoring Concurrent BIST Architecture using SRAM Cells

Authors:D. JAHNAVI, R. NIRANJAN

1319-1324

High-Throughput Hardware Implementation of Three Fish Block Cipher Encryption and Decryption on FPGA

Authors:P. GAYATHRI, KUNA SATEESH, CHERUKUPALLI NAVYA

1325-1329

Design of A Nano-Scale CMOS Inverter with Symmetric Switching Characteristics using Particle Swarm Optimization Algorithm

Authors:P. GAYATHRI, KUNA SATEESH, GADAM SRIKANTH

1330-1334

Efficient Adaptive Hold Logic Reliable Multiplier using Variable Latency Design

Authors:M. BHAVANA, DEVARAJ

1335-1339

An Efficient Carry Select Adder with Optimized Area and Delay by using AOI Logic

Authors:G.KAMAKSHI, M.SANDHYARANI

1340-1344