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Submission Open for February-2018
Last Date of Submission :
20th, February-2018
Acceptance Notification :

After Peer Review

Last Date of Publication :
30th, February-2018
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IJVDCS 200

Implementation of a Design Synthesis for Evaluation of FPGA Designs with Mixed LUTs for Area Efficiency

Authors:SAMIYA AFROZE, G. ARUNA

1043-1046

 
IJVDCS 201

An Efficient Multiplier Design using Carry Skip Adder Operating Under A Wide Range of Supply Voltages Levels for High Speed & Low Power Appliance

Authors:ZAKIA FATIMA, K. PREMA LATHA

1047-1053

 
IJVDCS 202

Area And Power Efficient of PreEncoded Multipliers using NR4SD

Authors:E. BALA KRISHNA, TADIMARI RESHMA

1054-1058

 
IJVDCS 203

Design of Hybrid CA LFSR Based BIST Enabled UART

Authors:CH. ANUDEEP, S. K. SATHYANARAYANA

1059-1062

 
IJVDCS 204

Design and Implementation of Reverse Multiplier using Approximate Compressor

Authors:PENNAMAREDDY ASHOK, A. CHANDRABABU

1063-1068

 
IJVDCS 205

FPGA Implementation of Filtered Image using 2D Gaussian Filter

Authors:GORATI SAI THIRUMAL, P. SHANKAR, VADTHYAVATH VIJAYA

1069-1075

 
IJVDCS 206

Hardwae Secuity Challenge Beyond CMOS:Attacks and Remediez

Authors:VADTHYAVATH VIJAYA, P. SHANKAR, GORATI SAI THIRUMAL

1076-1081

 
IJVDCS 207

High Throughput Finite Field Multipliers using Redundant Basic for FPGA Implementation

Authors:S. PRASAD, CH. SATHYANARAYANA

1082-1086

 
IJVDCS 208

Real-time Implementation of the ViBe Foreground Object Segmentation Algorithm

Authors:P. SHANKAR, GORATI SAI THIRUMAL, N. DASHARATH

1087-1091

 
IJVDCS 209

A Humble Theory and Application for Logic Encryption

Authors:P. SHANKAR, GORATI SAI THIRUMAL, VADTHYAVATH VIJAYA

1092-1101

 

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IJATIR(www.ijatir.org) Date of Submission: 20th February-2018, Date of Publishing: 28th February-2018
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