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Submission Open for December-2017
Last Date of Submission :
20th, December-2017
Acceptance Notification :

After Peer Review

Last Date of Publication :
30th, December-2017
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IJVDCS 190

An Efficient Design of Quantum Circuits by Swap Gate Using N-Gate Lookhead

Authors:D. GIRIJA, T. SWARNALATHA

0984-0990

 
IJVDCS 191

A High Performance Radix10 Multiplication Architecture Based on Redundant BCD Codes

Authors:SINGIREDDY SURESH KUMAR, A. LEELAVATHI, A. MADHUSUDHANA RAO

0991-0996

 
IJVDCS 192

Implementation of Low Area & Power Reversible Gates and Testablity of One Dimensional Array of Molecular Cells

Authors:SIRLI RAMESH, G. UMA MADHURI

0997-1003

 
IJVDCS 193

Realization of Fused-Add Multiply (FAM) Operator using Optimized Booth Recoder

Authors:CHEEPURUPALLI ASHOK, ANANTHA RAO GONDU

1004-1009

 
IJVDCS 194

Optimization of Delay using Reverse Multiplier and Approximate 15-4 Compressor

Authors:M. GEETHA, P. PRAVEEN KUMAR

1010-1016

 
IJVDCS 195

A New Design and Implementation of Dual Use Power Lines for DFT

Authors:P. PAVITHRA, A. DEVAMANI

1017-1022

 
IJVDCS 196

An Integration of RRAM Memory with Non Volatile Luts in the Evaluation of FPGA ERA

Authors:ISMATH AMREEN, K. PREMA LATHA

1023-1027

 
IJVDCS 197

Low Voltage Low Power Design of Self Boosting 3T Gain Cell for Embedded DRAM Applications

Authors:AIYESHA BEGUM, K. PREMA LATHA

1028-1033

 
IJVDCS 198

An VLSI Implementation of Flipflops using Threshold Logic Gates for Low Power Applications

Authors:ASMA SULTANA, G. ARUNA

1034-1038

 
IJVDCS 199

Implementation of A Delay Efficient Adder with Adaptive Feedback Equalization

Authors:SYED SANA KHATIJA, G. ARUNA

1039-1042

 

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IJSETR(www.ijsetr.com) Date of Submission: 20th December-2017, Date of Publishing: 30th December-2017
IJIT(www.ijitech.org) Date of Submission: 20th December-2017, Date of Publishing: 30th December-2017
IJATIR(www.ijatir.org) Date of Submission: 20th December-2017, Date of Publishing: 30th December-2017
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