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Submission Open for Jan-Dec-2018
Last Date of Submission :
20th, November-2018
Acceptance Notification :

After Peer Review

Last Date of Publication :
30th, November-2018
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Volume6 ISSUE 1
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Volume6 ISSUE 1
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Volume6 ISSUE 1
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IJVDCS 81

Implementation of Modified Booth Multiplier for Power Critical Applications

Authors:NIRMALA T, CHENNAIAH M P

411-416

 
IJVDCS 82

VLSI Implementation of Fast Addition Using Quaternary Signed Digit Number System

Authors:K. BHAVANA, K. KEERTHANA, K. PRABHAKAR REDDY

417-422

 
IJVDCS 83

3D Integration of L2 Memory Design for Multi Core Processor

Authors:M. HARUN BASHA, S. YASMINE

423-426

 
IJVDCS 84

FPGA Implementation of Digital Down Convertor

Authors:YAMUANA K H, B. RAMESH NAIK

427-434

 
IJVDCS 85

Implementation of Power Optimized RISC Processor

Authors:BOBBARADA VIJAYA LAKSHMI, G. MOUNICA REDDY

435-439

 
IJVDCS 86

DASARI DIVYA1, G. ANUSHA2, K. VIJAYA PRASAD3

Authors:DASARI DIVYA, G. ANUSHA, K. VIJAYA PRASAD

440-445

 
IJVDCS 87

Design Single Error Correction Codes with Fast Decoding for Subset of Critical Bits

Authors:CH. DURGHA NAGESWARI, R. SUNIL, K. VIJAYA PRASAD

446-449

 
IJVDCS 88

Completely Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications

Authors:M. PRAGNA, S. BAVANI, K. VIJAYA PRASAD

450-453

 
IJVDCS 89

Design of RNS Based Filter using Montgomery Multiplier and Kogge-Stone Adder

Authors:N. NANDINI, B. V. R. GOWRI

454-459

 
IJVDCS 90

Design of Power Optimized AES Based on Xilinx Software

Authors:P. MANI PRASAD, M. P. CHENNAIAH

0460-0464

 

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IJATIR(www.ijatir.org) Date of Submission: 20th November-2018, Date of Publishing: 30th November-2018
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