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Submission Open for Jan-Dec-2018
Last Date of Submission :
20th, September-2018
Acceptance Notification :

After Peer Review

Last Date of Publication :
30th, September-2018
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Volume6 ISSUE 1
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IJVDCS 61

Implementing A Full Adder/ Full Subtractor Using Parity Conserving Reversible Gates

Authors:Y. LAHARI, K. VENKATESH, P. PAVITHRA, S. SIREESHA, P. NAGARAJU

309-315

 
IJVDCS 62

Secured Electronic Voting Machine by using Biometric

Authors:CH. VENKATESWARLU, G. MOUNIKA, M. SRAVANI, B. RAJITHA, SK. SHAMEULLA

316-319

 
IJVDCS 63

Design of High Speed Reconfigurable Cordic

Authors:P. GOWTHAMI, K. VIJAYA PRASAD

320-323

 
IJVDCS 64

Design And Analysis of Approximate Floating-Point Adders

Authors:V. JYOTHSNA, S. BHAVANI, K. VIJAYA PRASAD

324-330

 
IJVDCS 65

Highly Efficient Decoder Architecture for Polar Codes

Authors:M.VINODE KUMAR, R.SUNIL, K. VIJAYA PRASAD

331-335

 
IJVDCS 66

A Modified Partial Product Generator for Redundant Binary Multipliers

Authors:G. SRUJANA, G. ANUSHA, K. VIJAYA PRASAD

336-340

 
IJVDCS 67

Arithmetic Algorithms for Higher Precision using Floating-Point Expansions

Authors:K.VENKATA ANUSHA, P. NAGA SRIKANTH, K. VIJAYA PRASAD

341-344

 
IJVDCS 68

Design of Error Free Parallel FFTs using Error Correction Codes And Parseval Checks

Authors:U. KRUPA, A. NAGA HIMAJA, K. VIJAYA PRASAD

345-349

 
IJVDCS 69

Design of Hybrid LUT/Multiplexer for CLB Blocks In Fpga Logic Architectures

Authors:B.VANAJA, M.VAISHNAVI, K. VIJAYA PRASAD

350-355

 
IJVDCS 70

Memory-Reduced Turbo Decoding Architecture

Authors:B. RAVI KIRAN, K. VIJAYA PRASAD

356-361

 

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IJIT(www.ijitech.org) Date of Submission: 20th September-2018, Date of Publishing: 30th September-2018
IJATIR(www.ijatir.org) Date of Submission: 20th September-2018, Date of Publishing: 30th September-2018
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