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Submission Open for April-2018
Last Date of Submission :
20th, April-2018
Acceptance Notification :

After Peer Review

Last Date of Publication :
30th, April-2018
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IJVDCS 51

An Enhanced Low-Power and High-Speed Frequency Multiplier for A DLL-Based Clock Generator

Authors:K. SUNIL KUMAR, S. HIMA BINDU, R. DIVYA PRATYUSHA, M. KOUSHIK SHARMA, M. HARISH

261-264

 
IJVDCS 52

Design and Analysis of an RSD Based ECC Processor

Authors:K. SUNIL KUMAR, S. SAI PRASANNA KUMAR, S. SAGAR GANESH REDDY, G. V. S. SANDEEP, B. RAJESH

265-270

 
IJVDCS 53

Processing Twin Data Streams for MIMO Through A Normal I/O Order Radix-2 FFT Architecture

Authors:BOLLU HARSHA SRI LEKHA, M. RAMBABU

271-274

 
IJVDCS 54

Improved 64-Bit Radix-16 Booth Multiplier Based On Partial Product Array Height Reduction

Authors:SALMA, SUNIL BABU

275-279

 
IJVDCS 55

Design And Implementation of FM0/Manchester Encoder Using Sols Technique

Authors:D. PRASANNA KUMAR, K. ASHOK KUMAR

280-285

 

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