Hybrid Multiplexer FPGA Logic Architectures

Authors:CHEEPURUPALLI SANTOSH, V. SIVA BHASKAR

100-104

Realization of Pulsed Latches Based Shift Register for Power Critical Applications

Authors:YERRA KRANTHI KUMAR, S.S.KIRAN, B. SANGEETH KUMAR

105-109

Implementation Low Power And High Performance Carry Select Addition Using BEC

Authors:PATHI MANASA, A. J PRASAD ABBADASARI, B. SANGEETH KUMAR

110-115

Implementation of Low Power Test Data Volume using LPLFSR And Hybrid Models

Authors:VILLURI DIVYARAMALAVANYA, T. GANGADHARA RAO

116-122

Realization of Cost Effective FIR Filter for Power Critical Applications

Authors:PADALA BHUPA REDDY, G.V.K.S. PRASAD

123-127

Design and Implementation of Digital Code Lock

Authors:Y. SURYAARJUNA RAO, M. K. CHANDRASEN

128-132

Fault Tolerant Parallel Filter Based On Error Correction Codes

Authors:G. SIVA KUMAR, T. R. PRASUNA BARRE

133-137

Design and Implementation of FFT using CMOS Cascage Current Mirror

Authors:TRIPARAGIRI RAVI, V. NANCHARAIAH

138-142

Non-Redundant Signed Digit Encoding by using Modified Booth Encoder

Authors:SATYAVENI POTHALA, S. V. SUDHEER KUMAR

143-148

VLSI Implementation of MIMO-OFDM for Low Power Applications

Authors:G. GOVINDA RAJU, Y. APPARAO

149-153