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Submission Open for Jan-Dec-2019
Last Date of Submission :
20th, January-2019
Acceptance Notification :

After Peer Review

Last Date of Publication :
30th, January-2019
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IJVDCS 91

Implementation of Area Optimized QCA based Adder

Authors:G. ANUSHA, SHAIK EKBAL ALI

465-469

 
IJVDCS 92

An Unified Algorithm Transactions for Implementation of Reconfigurable Cordic

Authors:PATTILA BHARAT KUMAR, D. LOKESH

470-476

 
IJVDCS 93

Implementation of Carry Skip Adder for Large Voltage Ranges

Authors:VUDAYANA PRIYANKA, D. LOKESH

477-481

 
IJVDCS 94

Implementing Low Power in Field Test for Permanent Faults in FIFO Buffers of Network On Chip Router And Inter Connect Testing

Authors:DUPPALA SANDEEP, D. LOKESH

482-484

 
IJVDCS 95

Implementation of High-Level Optimization Techniques for Low-Power Multiplier Design using Modified Booth

Authors:G. SAIPRASANNA, NANDINI MADINENI, M. G. MAHESH

485-489

 
IJVDCS 96

Implementation of Large Size Multipliers using MAC Adders and Higher Order 9:3 Compressors

Authors:M. MANJULA, NANDINI MADINENI, M. G. MAHESH

490-493

 
IJVDCS 97

Design and Implementation of 64-bit High Speed And Low Latency Vedic Multiplier

Authors:T. THANZEEM KHANAM, S. EKBAL ALI

494-498

 
IJVDCS 98

Implementation of High Speed Constant Multiplication

Authors:G. DIVYA TEJA, SK. UMAR FARUQ

499-503

 
IJVDCS 99

Implementation of High Speed 64-Bit Hybrid Adder

Authors:M. SINDHU, SK. UMAR FARUQ

504-507

 
IJVDCS 100

Low Complexity S-Box Architecture for Memory Applications

Authors:K. D. L. PRASAD, CH. LOKNADH

508-510

 

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